Simulating a FIFO utilizing QuestaSim
– // high module with inputs/outputs – module high (enter clk, rst, – output rdempty, wrfull, – output [7:0] data_out); – – //wires every sign – – logic clk_25, clk_100; // 25MHz and 100 MHz clocks – logic flag_locked; – logic fifo_aclr; – – assign fifo_aclr = !flag_locked; // aclr…