Hiya guys, I’ve posted one query about LVDS in Programmable Units group. Right here is the hyperlink: https://community.intel.com/t5/Programmable-Devices/Why-do-i-get-this-error-when-I-use-lvds/m-p/1619233/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExaN1lUQlI2VDRQNk5JfDE2MTkyMzN8U1VCU0NSSVBUSU9OU3xoSw#M97015
We’re holding testing and debugging our {hardware} with Cyclone 10 GX gadgets now. So there are a number of different issues, which want you assist.
1. The termination constrain choice:
In our case, there are three completely different LVDS enter sign sorts.
1). ADC output differential pairs;
2). LVDS interconnection between different FPGAs. On C10GX aspect is LVDS-RX.
3). Exterior pulse enter pairs.
The above first two gadgets, we all know the way to add on-chip termination, which is, for instance of ADC, input_termination differential constrain as following.
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_A
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_A
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_B
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_B
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_C
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_C
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D0_D
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_D1_D
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_DCO
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to PartA_FCOWe attempt to add identical constrain for above merchandise 3), nonetheless, it can work incorrectly with this constrain. However it could work nicely once we add the next constrain to them:
set_instance_assignment -name XCVR_C10_RX_TERM_SEL R_R1 -to CBA_TRIGGER_3 -entity sep_cs_relay_top
set_instance_assignment -name XCVR_C10_RX_TERM_SEL R_R1 -to CBA_TRIGGER_2 -entity sep_cs_relay_top
#set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CBA_TRIGGER_3 -entity sep_cs_relay_top
#set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to CBA_TRIGGER_2 -entity sep_cs_relay_topThis exterior pulse sign is LVDS differential normal, FPGA logic solely makes use of it as easy set off pulse, intead of excessive velocity serial information switch. Might anybody clarify what is the purpose for this?
2. For ADC serial information deserialize, we applied bit slip operate. You knonw, above ADC has whole 8 LVDS channels. So we generated 8 pulse alerts and assigned them to every bit slip management enter. However the query is that solely LSB was assigned succesfully. It signifies that solely the LSB of bit slip management alerts was energetic and it could management for all 8 LVDS channels alignment. Why solely the LSB bit slip is required for this operate?
