I additionally offers you my sdc file:
## Generated SDC file “R_fcnt_test.out.sdc”
## Copyright (C) 2018 Intel Company. All rights reserved.
## Your use of Intel Company’s design instruments, logic features
## and different software program and instruments, and its AMPP companion logic
## features, and any output information from any of the foregoing
## (together with gadget programming or simulation information), and any
## related documentation or info are expressly topic
## to the phrases and situations of the Intel Program License
## Subscription Settlement, the Intel Quartus Prime License Settlement,
## the Intel FPGA IP License Settlement, or different relevant license
## settlement, together with, with out limitation, that your use is for
## the only function of programming logic units manufactured by
## Intel and bought by Intel or its approved distributors. Please
## discuss with the relevant settlement for additional particulars.
## VENDOR “Altera”
## PROGRAM “Quartus Prime”
## VERSION “Model 18.1.0 Construct 625 09/12/2018 SJ Lite Version”
## DATE “Mon Sep 30 20:02:41 2024”
##
## DEVICE “5CSEBA6U23I7”
##
#**************************************************************
# Time Info
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}]
create_clock -name {fin} -period 12500.000 -waveform { 0.000 6250.000 } [get_ports {fin}]
create_clock -name {altera_tck} -period 1000.000 -waveform { 0.000 500.000 } [get_ports {altera_reserved_tck}]
create_clock -name {altera_tdo} -period 10.000 -waveform { 0.000 5.000 } [get_ports {altera_reserved_tdo}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {gate} -source [get_ports {clk}] -divide_by 50000 -master_clock {clk} [get_keepers gate]
create_generated_clock -name {fin_div2} -source [get_ports {fin}] -divide_by 2 -master_clock {fin} [get_pins q]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -hold 0.380
#**************************************************************
# Set Enter Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {clk}]
set_input_delay -add_delay -clock [get_clocks {fin}] 0.000 [get_ports {fin}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[0]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[1]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[2]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[3]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[4]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[5]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[6]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[7]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[8]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[9]}]
#**************************************************************
# Set Clock Teams
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {fin}] -to [get_clocks {clk}]
set_false_path -from [get_clocks {fin}] -to [get_clocks {gate}]
set_false_path -from [get_clocks {fin_div2}] -to [get_clocks {clk}]
set_false_path -from [get_clocks {fin_div2}] -to [get_clocks {gate}]
set_false_path -from [get_ports {rst_n}] -to [all_registers]
set_false_path -from [get_ports {altera_reserved_tck altera_reserved_tdi altera_reserved_tdo altera_reserved_tms}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Most Delay
#**************************************************************
#**************************************************************
# Set Minimal Delay
#**************************************************************
#**************************************************************
# Set Enter Transition
#**************************************************************
